In the prior art, clock is recovered from incoming data under circumstances where a parallel clock cable is not economical or where clock skew makes a separate clock line unfeasible.
Phase locked loops, frequency locked loops and phase and frequency locked loops are known in the prior art and have been utilized for clock recovery. An exemplary construction of devices of this type is shown in FIG. 13. Incoming data is compared with the output of a voltage controlled oscillator 1300 in a phase and/or frequency comparator 1310. An error voltage is generated at the output of the comparator 1310 which represents the difference in phase or frequency or both of the two signals. That error voltage then is utilized to control the frequency of the VCO 1300 to bring it into frequency and/or phase-lock with the incoming data stream. The output is a clock signal that is frequency and/or phase locked with the incoming data.
Voltage controlled oscillators used in frequency and phase-lock loops have a problem in that they accumulate jitter. That is, a phase transition is based on a previous transition and therefore, if the previous transition is off, the next one will be, too. Further, if each transition is off slightly because of jitter, since the transition is based on a previous transition, the phase error will accumulate.
VCO's also have the problem that a certain amount of time is required for them to adjust to changes in the input signal. The speed with which a VCO tracks changes in the incoming signal is a function of bandwidth. At very high bandwidths, the rate of change will be very fast, whereas at lower bandwidths, the change will be much slower. Typically, high bandwidths are difficult to achieve in VCO's.
Further, VCO's are subject to frequency change as a result of variations in supply voltages. When the supply voltage changes, the frequency of the VCO changes until the feedback loop compensates.
Delay lock loops are also known in the prior art. An exemplary delay lock loop is shown in FIG. 14. Incoming data is routed to a voltage control delay line 1400. The output of the voltage controlled delay line 1500 is returned to one input of a phase comparator 1410. The other input of the phase comparator 1410 receives an incoming data stream. The phases of the two data streams are compared in the comparator and an error voltage is generated and applied to a low pass filter 1420, the output of which is utilized to control the amount of delay to be inserted by the voltage control delay line 1400.
Delay lock loops have two important advantages over phase-lock loops. First, because the delay line has no "memory," its transfer function is a constant, thereby yielding a first-order open-loop transfer function for the entire system (for a first-order LPF). Consequently, delay lock loops have much more relaxed tradeoffs among gain, bandwidth and stability. Second, delay lines typically introduce much less jitter than oscillators. Intuitively, this is because delaying a signal entails much less uncertainty than generating it. From another point of view, noise injected into a delay lock loop disappears at the end of the delay line, whereas it is recirculated when a voltage controlled oscillator is used.
Voltage control delay lines of a type used in a delay locked loop are also known. An exemplary delay line is shown in FIG. 15. A voltage control delay line consists of a plurality of delay elements 15-1-15-N. The number of delay elements effectively inserted into the signal path between V.sub.in and V.sub.out is a function of the control input voltage. As the input voltage changes, the number of delay elements effectively inserted in the path increases or decreases.